Semiconductor memory device with resistive power supply connection

ABSTRACT

In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.

This application is a Continuation of application Ser. No. 08/208,596,filed Mar. 11, 1994, now abandoned, which was a Divisional applicationof application Ser. No. 07/702,496, filed May 20, 1991, now U.S. Pat.No. 5,321,658.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, such asa dynamic random-access memory (RAM). The invention aims at reducing thedifference in the operation margin between the memory cell arrays due tothe line resistance (impedance) of the power supply line, and noises dueto charging and discharging currents during the operation of the senseamplifier.

BACKGROUND OF THE INVENTION

An example of prior art semiconductor memory device of this type isshown in FIG. 1. Its configuration will now be described with referenceto the drawings.

FIG. 1 shows the structure of the prior art semiconductor memory device,e.g., dynamic RAM.

This semiconductor memory device has a power supply pad 1 for the groundpotential (Vss), and a power supply pad 2 for the power supply potential(Vcc). Connected to the Vss and Vcc power supply pads 1 and 2 are powersupply lines 3 and 4, respectively. Connected between the power supplylines 3 and 4 are a plurality of memory cell arrays 10-1 to 10-N. Thenumber of the memory cell arrays 10-1 to 10-N is 8, for example, in thecase of a 4 Mbit dynamic RAM. Both supply lines 3 and 4 include lineresistance r.

Each of the memory cell arrays 10-1 to 10-N comprises a memory cellmatrix 10a of 512 Kbits, for example, a sense amplifier group 10b, and acontrol circuit 10c for controlling the sense amplifiers 10b. Althoughnot illustrated, peripheral circuits, such as an input circuit forinputting a signal from the outside of the chip, an output circuit foroutputting information of the memory cell to the outside, and a writingcircuit for writing data from the outside into the memory cells are alsoconnected to the Vss pad 1 and the Vcc pad 2.

In this semiconductor memory device, when a power supply voltage issupplied from the Vss pad 1 and the Vcc pad 2, the power supply voltageis applied via the power supply lines 3 and 4 to the memory cell arrays10-1 to 10-N. Then the memory cell arrays 10-1 to 10-N operate, andaccessing, i.e., data reading or data writing, is performed.

In this type of the semiconductor memory device, as the memory capacityis increased, e.g., up to several Mbits, the length of the conductor ofthe power supply lines (wiring conductors) 3 and 4 may be as long asseveral tens of millimeters, and the line resistance of the power supplylines 3 and 4 can be no longer neglected. The power supply lines 3 and 4disposed from the Vss pad 1 and the Vcc pad 2 and along the memory cellarrays 10-1 to 10-N are therefore formed of a material having a lowsheet resistance (such as aluminum) and their width is enlarged in orderto to reduce the resistance from the Vss pad 1 and the Vcc pad 2.

A specific example of a semiconductor memory device is shown in FIG. 2,and an example of the memory cell array in FIG. 2 is shown in FIG. 3.Identically labelled elements appearing in the different Figures referto one in the same element.

As illustrated in FIG. 2, a plurality of memory cell arrays 10-1 to 10-Nare connected between the power supply line 3 connected to the Vss pad 1and the power supply line 4 connected to the Vcc pad 2. The senseamplifiers in each memory cell array 10-1 to 10-N are connected to thepower supply line 3 via common nodes N1 supplying a sense latch signalSLN and sense amplifier drive n-channel MOS transistors (NMOStransistors) 11-1 to 11-N that are turned on and off by a control signalSN. The sense amplifiers in each memory cell array 10-1 to 10-N areconnected to the power supply line 4 via common nodes N2 supplying asense latch signal SLP and sense, amplifier drive p-channel MOStransistors (PMOS transistors) 12-1 to 12-N which are turned on and offby a control signal SP.

Also connected to the Vss pad 1 and the Vcc pad 2 are a plurality ofperipheral circuits 13-1 to 13-4 for controlling input and output of thesemiconductor memory device.

The memory cell arrays 10-1 to 10-N are identical to each other, and oneof them, the memory cell array 10-1 is taken up for further explanationwith reference to FIG. 3.

The memory cell array 10-1 comprises a memory cell matrix 10a, a senseamplifier group 10b comprising a plurality of sense amplifiers 10b₁ to10b_(P) and a control circuit 10c. The control circuit 10c comprises aplurality of word line drive circuits 30₁ to 30_(Q), precharge circuits31₁ to 31_(P), transfer gates 32₁ to 32_(P), and the like.

The memory cell matrix 10a comprises a plurality of word lines WL₁ toWL_(Q), and a plurality of pairs of bit lines BL₁, BL₁ to BL_(P),BL_(P), and memory cells 20₁₁ to 20_(PQ) connected at the intersectionsof the word lines and the bit lines. Each memory cell 20₁₁ -20_(PQ)includes a transistor 20a and a capacitor 20b. Connected to the bit linepairs BL₁, BL₁ to BL_(P), BL_(P) are sense amplifiers 10b₁ to 10b_(P).The sense amplifiers 10b₁ to 10b_(P) are activated by the sense latchsignals SLN and SLP on the common nodes N1 and N2, respectively, todetect and amplify the potential difference between each pair of bitlines, and is formed of two NMOS transistors 21a and 21b, and two PMOStransistors 21c and 21d.

The word line drive circuits 30₁ to 30_(Q) are connected to the wordlines WL₁ to WL_(Q). The word line drive circuits 30₁ to 30_(Q)respectively are responsive to the row decode selection signals XD₁ toXD_(Q) to vary the word lines WL₁ to WL_(Q) to the high level (Vcc) orto the low level (Vss). The precharge circuits 31₁ to 31_(P) areconnected to the pairs of bit lines BL₁, BL₁ to BL_(P), BL_(P) forprecharging the corresponding pairs of the bit lines to a referencevoltage VR responsive to a precharge signal EQ. The transfer gates 32₁to 32_(P) are connected to the pairs of bit lines BL₁, BL₁ to BL_(P),BL_(P) and are turned on and off by a column decode selection signal YD₁to YD_(P) to transfer data on the corresponding pairs of bit lines tocomplementary data lines DB and DB.

FIG. 4 is a waveform diagram for explaining the operation of the circuitof FIG. 3. The operation of FIG. 2 and FIG. 3 will now be described withreference to FIG. 4.

Let us consider the operation of reading data "1" that is stored in thememory cell 20₁₁ in FIG. 3.

In FIG. 4, the precharge signal EQ of the precharge circuits 31₁ and31_(P) precharging the pairs of bit lines BL₁, BL₁ to BL_(P), BL_(P) tothe reference voltage VR (=1/2.Vcc) is lowered from the high level ("H")to the low level to put an end to the precharge. Then, the word line WL₁is raised to the high level by the word line drive circuit 30₁ to whichthe column decode select signal XD₁ is input. Then the data "1" in thememory cell 20₁₁ is output to the bit line BL₁, creating a slightpotential difference between the pair of bit lines BL₁, BL₁.

After the word line WL₁ is raised, the control signal SN is raised tothe high level and the control signal SP is lowered to the low level.The sense amplifier drive NMOS transistor 11-1 and PMOS transistor 12-1are turned on, and the sense latch signals SLN and SLP on the commonnodes N1 and N2 precharged to the reference voltage VR, through a pathnot illustrated, are varied to the Vss level and the Vcc level,respectively, so that the sense amplifiers 10b₁ to 10b_(P) operate. Whenthe sense amplifiers 10b₁ to 10b_(P) operate, a discharging current I₁(see FIG. 3) flows from the bit line BL₁ as well as other bit lines BL₂to BL_(P), via the NMOS transistors 21a of the respective senseamplifiers 10b₁ to 10b_(P), the common node N1, and the NMOS transistor11-1 to the power supply line 3, and a charging current I₂ (see FIG. 3)flows via the common node N2, and the PMOS transistor 21d to the bitlines BL₁ to BL_(P) through the PMOS transistor 12-1 from power supplyline 4. By the sensing action of the sense amplifiers 10b₁ to 10b_(P),slight potential differences on the pairs of bit lines BL₁, BL₁ toBL_(p), BL_(P) are detected and amplified.

After adequate amplification by the sense amplifiers 10b₁ to 10b_(P),the column decode select signal YD₁ is raised from the low level to thehigh level and the transfer gate 32₁ is turned on, and the potential onthe pair of the bit lines BL₁ and BL₁ is transferred to the data buslines DB and DB. Data is thus read from the desired memory cell 20₁₁.

In this type of semiconductor memory device, the sense latch signals SLNand SLP are made to operate in a higher speed in order to perform thesensing operation at a higher speed. This can be achieved by increasingthe size of the NMOS transistors 11-1 to 11-N and the PMOS transistors12-1 to 12-N, or the power supply lines 3 and 4 shown in FIG. 2, and theconductors for the common nodes N1 and N2 shown in FIG. 2 are made ofmetal (e.g., aluminum) having a lower sheet resistance to decrease theresistance.

The above memory device however is associated with the followingproblems.

(a) In a semiconductor memory device of a large capacity on the order ofmegabits, the power supply lines 3 and 4 may be as long as 15 mm and theline resistance cannot be neglected. For instance, when the power supplylines 3 and 4 are made of aluminum having a low sheet resistance, thesheet resistance is 0.06 Ω when the film thickness is 600 angstroms. Ifthe conductor-length/conductor-width from the Vss pad 1 or the Vcc pad 2to the farthest memory cell array 10-N or 10-1 is 15 mm/100 μm, the lineresistance will be 0.06 Ω×15000/100=9 Ω.

With such a line resistance r, differences are created in the powersupply resistance from the Vss pad 1 or the Vcc pad 2 to the respectivememory cell arrays 10-1 to 10-N, and differences are created in theoperation margin between the memory cell arrays 10-1 to 10-N, and accessdelays and the like are also created.

(b) With the prior art semiconductor memory devices, it is possible toincrease the speed of the sensing operation by enlarging the size of thesense amplifier drive NMOS transistors 11-1 to 11-N and PMOS transistors12-1 to 12-N, or by using metal of a smaller sheet resistance for thepower supply lines 3 and 4 and the conductors for the common nodes N1and N2. However, increase of the sensing operation may be accompaniedwith the increase in the charging current I₂ and discharging current I₁,and substantial drop in the Vcc level on the power supply lines 4 and 3or substantial rise in the Vss level. (See FIG. 4.) When this drop orrise occurs, it acts as a noise giving an adverse effect on theoperation after the sense latch, causing access delay or varying thecircuit threshold value. Specifically, reduction in the TTL margin ofthe initial-stage circuit provided in the peripheral circuits 13-1 to13-4 and operating responsive to TTL level (transistor-transistor logiclevel) or the like may occur.

(c) A further problem is associated with the differences between in theline resistances for the respective memory cell arrays.

As illustrated in FIG. 2, line resistance r is present on the powersupply lines 3 and 4, so the power supply resistances at the junctionswith the memory cell arrays 10-1 to 10-N differ from each other. Forinstance, with respect to the memory cell array 10-1, the resistance ofthe power supply line 3 at the junction with the NMOS transistor 11-1 issmall, and the resistance of the power supply line 4 at the junctionwith the PMOS transistor 12-1 is large. A large Vss noise is created inthe vicinity of the Vss pad 1, and the Vcc noise in the vicinity of theVcc pad 4 is small. In contrast, when the memory cell array 10-N is madeto operate the Vss noise in the vicinity of the Vss pad 1 is small, andthe Vcc noise in the vicinity of the Vcc pad 2 is large. As a result,the noises in the vicinities of the power supply pads 1 and 2 differdepending on which of the memory cell arrays 10-1 to 10-N is made tooperate.

The noises are transmitted via the power supply pads 1 and 2 to thepower supply lines 112 and 122 adversely affecting the peripheralcircuits connected thereto. In particular, in the input initial-stagecircuits receiving RAS (row address strobe), CAS (column addressstrobe), and other control signals of the TTL level, and operating onthe TTL level (not shown), when the memory cell array 10-1 is made tooperate, the Vss noise is large, so the high-level-side margin in theinput initial-stage circuits declines. When the memory cell array 10-Nis made to operate, the Vcc noise is large, so the low-level-sidemargins declines. Thus, depending on which of the memory cell arrays10-1 to 10-N operates, the operation margin of the input initial-stagecircuits occur may differ and decline, and, as a result, malfunctions ofthe peripheral circuits including the input initial-stage circuits canoccur.

SUMMARY OF THE INVENTION

The invention aims at solving the problems in the prior art.

An object of the present invention is to reduce the difference in theoperation margin due to the power supply resistance of the memory cellarrays.

Another object of the invention is to reduce the difference in theoperation margin due to the increase of the charging and dischargingcurrents during the sense amplifier operation.

A further object of the invention is to reduce the difference betweenthe noises in the vicinity of the power supply pads which differdepending on the memory cell array that operates, thereby to reduce theadverse effects such as malfunctions of the peripheral circuitsincluding the input initial-stage circuits.

In order to solve the above problem, a semiconductor memory deviceaccording to a first aspect of the invention comprises a plurality ofmemory cell arrays, in which a potential difference between a pair ofbit lines to which memory cells are connected is detected and amplifiedby a sense amplifier operating responsive to a sense latch signal on acommon node, and the memory cells are connected via a power supply lineto a power supply, characterized in that:

the power supply line comprises a main line disposed along the pluralityof memory cell arrays and an auxiliary line disposed within each memorycell array; and

the main line and the auxiliary line are connected to each other via aresistive element having a resistance larger than the resistance overthe main line from the power supply to the memory cell array locatedfarthest from the power supply.

With the above arrangement, the power supply voltage supplied from thepower supply is supplied via the main line and respective resistiveelements, and further via the auxiliary lines to the memory cell arrays.The resistive elements are set to have a larger resistance than the lineresistance over the main line, so the line resistance is effectivelyneglected, and the power supply resistance of each memory cell array isdetermined by the resistance of the resistive element. Accordingly, thedifference between the power supply resistances for the memory cellarrays are reduced, and the difference in the operation margin of thememory cell arrays is reduced. As a result, setting of the timing ofcontrol for accessing or the like is facilitated.

A semiconductor memory device of a second aspect of the invention ischaracterized in that:

the common node in each memory cell array is connected to the powersupply line via a series connection of a resistive element and a senseamplifier drive transistor which is turned on and off by a controlsignal.

With the above arrangement, when the sense amplifier drive transistor isturned on, the sense latch signal output from the transistor is appliedto the sense amplifiers via the common nodes in the memory cell arrays,and the sense amplifiers operate to detect and amplify the potentialdifference between the pair of the bit lines. Charging and dischargingcurrents that flow between the sense amplifiers and the power supplylines are however reduced by the resistive elements, and the variationin the power supply potential is reduced, and the operation margin isreduced due to the reduction in noise.

The semiconductor memory device of the second aspect of the inventionrecited above may further be provided with a switching device which isconnected in parallel with the resistive element, and is turned on andoff by a switching signal delayed from the control signal by apredetermined time.

The switching device is turned on, during the operation of the senseamplifier, responsive to the switching signal, being delayed from thesense amplifier drive transistor by the predetermined time. Accordingly,variation in the charging and discharging currents flowing through thesense amplifier drive transistor is distributed, so the attendant powersupply noise is reduced, and the data transfer speed is improvedpreventing the reduction in the speed of the operation due to theinsertion of the resistive element.

A semiconductor memory device of a third aspect of the inventioncomprises:

a plurality of memory cells connected at the intersections of aplurality of word lines and a plurality of pairs of bit lines;

a plurality of sense amplifiers for detecting and amplifying thepotential difference between the pair of bit lines;

a plurality of transistors turned on by a control signal and eachconnecting a predetermined number of the plurality of sense amplifiersto a power supply line;

wherein said plurality of transistors have mutual conductances whichdiffer depending on the resistance of the power supply line.

With the above arrangement, in the vicinity of the power supply padwhere the power supply resistance is small, the mutual conductance ofthe transistor is made small, and where the power supply resistance islarge, the mutual conductance of the transistor is made large.Accordingly, the on-resistance of the transistor connected at thelocation where the power supply resistance is small is large, so thecharging and discharging currents which flow instantly between the senseamplifiers and the power supply lines are restrained, and the noisescreated in the power supply lines are reduced.

In addition, since the mutual conductance of the transistor connected toa location where the power supply resistance is considerably large, thecharging and discharging currents which flow instantly between the powersupply lines and the sense amplifiers is decreased, and the differencein the noise due to the difference of the memory cell array thatoperates is reduced. As a result, the Vcc noise and the Vss noise arekept constant whichever transistor is made to operate, and thedifference and lowering of the operation margin in the peripheralcircuit including the input initial-stage circuits can be prevented, andthe above problem is therefore solved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the configuration of the semiconductormemory device in the prior art.

FIG. 2 is a diagram showing the configuration of the semiconductormemory device in the prior art.

FIG. 3 is a circuit diagram showing the memory cell array in FIG. 2.

FIG. 4 is a waveform diagram for explaining the operation of thesemiconductor memory device of FIG. 3.

FIG. 5 is a diagram showing the configuration of the semiconductormemory device of a first embodiment of the invention.

FIG. 6 is a diagram showing the configuration of the semiconductormemory device of a second embodiment of the invention.

FIG. 7 is a diagram showing the configuration of the semiconductormemory device of a third embodiment of the invention.

FIG. 8 is a diagram showing the memory cell array in the semiconductormemory device of FIG. 7.

FIG. 9 is a waveform diagram for explaining the operation of thesemiconductor memory device of FIG. 8.

FIG. 10 is a diagram showing the configuration of the semiconductormemory device of a fourth embodiment of the invention.

FIG. 11 is a waveform diagram for explaining the operation of thesemiconductor memory device of FIG. 10.

FIG. 12 is a diagram showing the configuration of the semiconductormemory device of a fifth embodiment of the invention.

FIG. 13 is a waveform diagram for explaining the operation of thesemiconductor memory device of FIG. 12.

FIG. 14 is a diagram showing the pertinent portion of the semiconductordevice of a sixth embodiment of the invention.

FIG. 15A and FIG. 15B are waveform diagrams for explaining the operationof the semiconductor memory device of FIG. 14 and that of the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 5 is a schematic diagram showing a semiconductor memory device,e.g., a dynamic RAM, of a first embodiment of the invention.

This semiconductor memory device is provided with a Vss power supply pad51 and a Vcc power supply pad 52. Connected to the power supply pad 51is a Vss power supply line (interconnection) 53. Connected to the powersupply pad 52 is a power supply line 54. A plurality of memory cellarrays 60-1 to 60-N are connected between the power supply lines 53 and54.

The power supply line 53 on the Vss side comprises a main line 53adisposed along the memory cell arrays 60-1 to 60-N from the Vss pad 51,and auxiliary lines 53b-1 to 53b-N disposed within the memory cellarrays 60-1 to 60-N, and the main lines 53a and the auxiliary lines53b-1 to 53b-N are mutually connected via resistive elements R11 to R1N.Similarly, the power supply line 54 on the Vcc side comprises a mainline 54a disposed along the memory cell arrays 60-1 to 60-N from the Vsspad 52, and auxiliary lines 54b-1 to 54b-N disposed within the memorycell arrays 60-1 to 60-N, and the main lines 54a and the auxiliary lines54b-1 to 54b-N are mutually connected via resistive elements R21 to R2N,The main lines 53a and 54a have a line resistance (impedance)distributed along itself.

Each of the memory cell arrays 60-1 to 60-N comprises a memory cellmatrix 60a consisting of a matrix arrangement of memory cells at theintersections of a plurality of word lines and bit line pairs, and asense amplifier group 60b comprising a plurality of sense amplifiers fordetecting and amplifying the slight potential differences between thecorresponding bit line pairs, and a control circuit 60c for controllingthe operation of the memory cell array.

The memory cell matrix 60a, the sense amplifier group 60b and thecontrol circuit 60c may be similar to those shown in FIG. 3.

An input circuit for inputting signals from the outside of the chip, anoutput circuit for outputting information of the memory cells to theoutside, and a writing circuit for writing data from the outside in thememory cells, which are not shown, are also connected to the Vss pad 51and the Vcc pad 52.

When the power supply voltage is applied via the Vss pad 51 and the Vsspad 52, the power supply voltage is supplied via the power supply lines53 and 54, the resistive elements R11 to R1N and R21 to R2N, to thememory cell arrays 60-1 to 60-N. The memory cell arrays 60-1 to 60-N arethen brought into the operative condition, and the data reading orwriting is performed on the memory cell matrix 60a in the memory cellarrays 60-1 to 60-N.

Let us now consider the Vss power supply resistance within memory cellarrays 60-1 to 60-N. For the first memory cell array 60-1, it is R11+r;for the second memory cell array 60-2, it is R12+2r, for the N-th memorycell array, it is R1N+Nr. In order to reduce the difference in the Vsspower supply resistance between the memory cell arrays 60-1 to 60-N, theratio of the resistance Nr of the line to the resistance of theresistive element R1N should be reduced, i.e., the resistance Nr of theline be reduced and the resistance of the resistive element R1N beenlarged to reduce the effects of the line resistance r.

As a way of reducing the line resistance Nr, if the number of the memorycell arrays 60-1 to 60-N is fixed, the line resistance r of the mainline 53a should be reduced. To reduce the line resistance r, the widthof the line should be increased or the sheet resistance of the lineshould be reduced. Let us assume a situation in which the lineresistance Nr is set at a certain value. In this case, the resistance ofthe resistive element R1N is set larger than the line resistance Nr,then the line resistance Nr can effectively be neglected, so thedifference in the Vss power supply resistance between the memory cellarrays 60-1 to 60-N can be reduced.

The resistance R1i (i=1 to N) may be so set that:

    R11=R12= . . . R1N>>Nr

or

    R11+r≈R12+2r≈ . . . ≈R1N+Nr

In either case, the resistance R1i can be realized by forming theresistive elements R11 to R1N of a material having a large sheetresistance (such as polysilicon, tungsten-polycide, or the like), ratherthan aluminum which is a metal line. The above measure of reducing thedifference between the Vss power supply resistance can be also appliedto the Vcc power supply resistance.

By inserting the resistive elements R11 to R1N and R21 to R2N betweenthe main lines 53a and 54a, respectively and the auxiliary lines 53b-1to 53b-N and 54b-1 to 54b-N, so that the power supply resistance of thememory cell arrays 60-1 to 60-N is determined effectively by theresistive elements R11 to R1N and R21 to R2N, the difference in thepower supply resistance between the memory cell arrays can be reduced.

The insertion of the resistive elements R11 to R1N and R21 to R2Nincreases the power supply resistance for the memory cell arrays 60-1 to60-N. The circuit operation speed is therefore lowered by a certaindegree. But as the provision of the resistive elements R11 to R1N andR21 to R2N reduces the difference in the operation margin between thememory cell arrays 60-1 to 60-N, setting of the control timing for thedata reading and writing is facilitated, and this merit is greater thanthe demerit of the reduction in the operation speed.

Second Embodiment

FIG. 6 schematically illustrates a semiconductor memory device of asecond embodiment of the invention. Elements common with FIG. 5 aregiven identical reference marks.

The difference of this semiconductor memory device from FIG. 5 is thatan internal power supply generating circuit 61 is connected to the Vsspad 51, and the output node of the internal power supply generatingcircuit 61 is connected to the main lines 53a and 54a of the powersupply conductors 53 and 54.

The internal power supply generating circuit 61 receives the powersupply voltage from the Vcc pad 52, causes a predetermined voltage drop,and supplies a power supply voltage of a lower level than Vcc to themain lines 53a and 54a. It is formed of a resistor voltage divider, MOStransistors, or the like, and serves as a power supply circuit.

Providing the above-described internal power supply generating circuit61, and driving the memory matrix 60a within the memory cell arrays 60-1to 60-N with the lower level power supply voltage, deterioration of thememory elements can be prevented. Moreover, with the provision of theresistive elements R11 to R1N and R21 to R2N, the difference in theoperation margin between the memory cell arrays 60-1 to 60-N can bereduced, as in the first embodiment.

Third Embodiment

FIG. 7 shows a semiconductor memory device of a third embodiment of theinvention. Identical elements to those in FIG. 5 are denoted byidentical reference marks.

This semiconductor memory device is provided with common nodes N1 and N2which also correspond to the power supply auxiliary lines 53b and 54b inFIG. 5 and FIG. 6, and which serve to transfer the sense latch signalsSLN and SLP into the memory cell arrays 60-1 to 60-N. The common nodesN1 (power supply auxiliary line 53b) within the memory cell arrays 60-1to 60-N are connected via sense amplifier drive NMOS transistors 62-1 to62-N which are turned on and off by the control signal SN, and theresistive elements R1, to the power supply main line 53a, which isconnected to the Vss pad 51. Similarly, the common nodes N2 (powersupply auxiliary line 54b) within the memory cell arrays 60-1 to 60-Nare connected via sense amplifier drive PMOS transistors 63-1 to 63-Nwhich are turned on and off by the control signal SP, and the resistiveelements R2, to the power supply auxiliary line 54b, which is connectedto the Vcc pad 52.

Connected to the Vss pad 51 and the Vcc pad 52 are peripheral circuits64-1 to 64-4 for controlling input and output of the semiconductormemory device.

Like the embodiment of FIG. 5, each of the memory cell arrays 60-1 to60-N comprises a memory cell matrix 60a, sense amplifiers 60b and acontrol circuit 60c. Their details are shown in FIG. 8.

The illustrated memory cell array 60-1 comprises a memory cell matrix60a for storing data, a sense amplifier group 60b comprising a pluralityof sense amplifiers 60b₁ to 60b_(P) for detecting and amplifying thepotential difference between the pairs of bit lines, and a controlcircuit for controlling the memory cell array 60-1. This control circuitcomprises a plurality of word line drive circuits 80₁ to 80_(Q), aplurality of precharge circuits 81₁ to 81_(P), a plurality of transfergates 82₁ to 82_(P), and the like.

The memory cell matrix 60a is for storing data, and has a plurality ofword lines WL₁ to WL_(Q), a plurality of pairs of bit lines BL₁, BL₁ toBL_(P), BL_(P), and memory cells 70₁₁ to 70_(PQ) connected at theirintersections. The memory cells 70₁₁ to 70_(PQ) are each configured of aone-transistor memory cell which is formed of NMOS transistor 70a and acapacitor 70b.

Connected to the pairs of the bit lines BL₁, BL₁, to BL_(P), BL_(P) isthe sense amplifier group 60b. The sense amplifier group 60b iscomprised of a plurality of sense amplifiers 60b₁ to 60b_(P) whichdetect and amplify the potential differences between the pairs of thebit lines BL₁, BL₁ to BL_(P), BL_(P), and which are driven by the senselatch signals SLN and SLP on the common nodes N1 and N2. The senseamplifiers 60b₁ to 60b_(P) are each configured of a flip-flop comprisedof NMOS transistors 71a and 71b, and PMOS transistors 71c and 71dcross-coupled with the pairs of the bit lines BL₁, BL₁ to BL_(P),BL_(P).

The word line drive circuits 80₁ to 80_(Q) connected to the word linesWL₁ to WL_(Q) set the word lines WL₁ to WL_(Q) to the high level or thelow level responsive to the column decode select signal XD₁ to XD_(Q),and are formed of NMOS transistors 80a and 80b, and an inverter 80c. Theprecharge circuits 81₁ to 81_(P) connected to the pairs of bit linesBL₁, BL₁ to BL_(P) to BL_(P) precharge the bit lines BL₁, BL₁ to BL_(P),BL_(P) to the reference potential VR in accordance with the prechargesignal EQ, and are formed of NMOS transistors 81a and 81b. The transfergates 82₁ to 82_(P) connected to the pairs of bit lines BL₁, BL₁ toBL_(P) to BL_(P) transfer the information of the memory cells 70₁₁ to70_(PQ) to the complementary data lines DB, DB and are formed of NMOStransistors 82a and 82b which are turned on and off by the column decodeselect signals YD₁ to YD_(P).

FIG. 9 is a waveform diagram for explaining the operation of the circuitof FIG. 8. The operation of the semiconductor device of FIG. 7 and FIG.8 will now be described with reference to FIG. 9. In FIG. 9, thewaveforms in solid line represents the third embodiment and the brokenline represents the prior art.

Let us assume a situation in which data "1" which is stored in thememory cell 70₁₁ is read out.

During stand-by, the precharge signal EQ is at the high level ("H"), andthe precharge circuit 81₁ to 81_(P) are on, and the pairs of bit linesBL₁, BL₁ to BL_(P), BL_(P) are precharged to the reference potential VR.When reading is performed, the precharge signal EQ is lowered from thehigh level ("H") to the low level. The precharge circuits 81₁ to 81_(P)are then turned off, and the supply of the reference potential to thepairs of bit lines BL₁, BL₁ to BL_(P), BL_(P) is stopped to terminatethe precharge.

The word lines drive circuit 80₁ is then activated by the column decodeselect signal XD₁. The NMOS transistor 80a in the word line drivecircuit 80₁ is then turned on and the power supply main line 54a and theword line WL₁ are then conductive to each other. The word line WL₁ isthen raised from the low level ("L") to the high level. The NMOStransistor 70a in the memory cell 70₁₁ connected to the word line WL₁ isturned on, and the information "1" stored in the capacitor 70b is outputto the bit lines BL₁, and a slight potential difference is createdbetween each of the pairs of bit lines BL₁, BL₁. At the same time, othermemory cells 70₂₁ to 70_(P1) connected to the same word line WL₁ arealso activated and their data are transmitted to the respective bit linepairs BL₂, BL₂ to BL_(P), BL_(P).

When the control signals SN and SP are thereafter raised from the lowlevel ("L") to the high level ("H"), the sense amplifier drive NMOStransistors 62-1 to 62-N and 63-1 to 63-N are turned on, and the senselatch signals SLN on the common nodes N1 are varied to the low level viathe power supply main line 53a and the resistive elements R1, while thesense latch signals SLP on the common nodes N2 are varied to the highlevel via the power supply main line 54a and the resistive elements R2,so the sense amplifiers 60b₁ to 60b_(P) are activated.

The sense amplifiers 60b₁ to 60b_(P) detect slight potential differenceson the pairs of bit lines BL₁, BL₁ to BL_(P), BL_(P), and discharge thepotential on the bit line BL₁ to BL_(P) via the NMOS transistors 71a ofthe respective sense amplifiers 60b₁ to 60b_(P), and the dischargingcurrent I₁ (see FIG. 7) flows through the common node N1 and the NMOStransistor 62-1 and the resistive element R1 to the power supply mainline 53a. Concurrently, a charging current I₂ (see FIG. 7) flows throughthe power supply main line 54a, the resistive element R2, the PMOStransistor 63-1, the common node N2, and the PMOS transistor 71d of therespective sense amplifiers 60b₁ to 60b_(P), and by this chargingcurrent I₂ the bit line BL₁ to BL_(P) are charged, and the potentialdifferences on the pairs of bit lines BL₁, BL₁ to BL_(P), BL_(P) are areamplified.

After the potential differences on the pairs of bit lines BL₁, BL₁ toBL_(P), BL_(P) are fully amplified, the column decode select signal YD₁is raised from the low level to the high level. The NMOS transistors 82aand 82b in the transfer gate 82₁ are thereby turned on and the data onthe pair of bit lines BL₁, BL₁ is transferred to the data lines DB, DB.Reading of data from the memory cell 70₁₁ is thus achieved.

In this third embodiment, the drain of the NMOS transistor 62-1outputting the sense latch signal SLN is connected via the resistiveelement R1 to the power supply main line 53a on the Vss side, and thedrain of the PMOS transistor 63-1 outputting the sense latch signal SLPis connected via the resistive element R2 to the power supply main line54a on the Vcc side. Accordingly, by virtue of the resistive elements R1and R2, the discharging current I₁ and the charging current I₂ at thetime of operation of the sense amplifiers can be restrained as comparedwith the prior art. Thus, as shown in FIG. 9, the rise of the Vss leveland the fall of the Vcc level on the power supply main lines 53a and 54aare smaller than in the prior art.

Because the resistive elements R1 and R2 are provided, there is adisadvantage that the variation in the sense latch signals SLN and SLPand the potentials on the pairs of bit lines BL₁, BL₁ are more delayedthan in the prior art, but the rise in the Vss level and the fall in theVcc level are restrained, so the delays in the access time during theoperation of the circuit after the sense latch, and the degradation theoperation margin such as the TTL margin degradation can be prevented,and these merits are greater.

Fourth Embodiment

FIG. 10 shows the pertinent portion of the semiconductor memory deviceof a fourth embodiment of the invention. Elements identical to those inFIG. 7 are denoted by identical reference marks.

This semiconductor memory device differs from the third embodiment inthat the resistive elements R1-1 and R2-1 are respectively inserted onthe side of the sources of the sense amplifier drive NMOS transistors62-1 to 62-N and PMOS transistors 63-1 to 63-N, i.e., between the MOStransistors and the common nodes N1 and N2.

FIG. 11 shows the waveforms for explaining the operation of FIG. 10.Detailed explanation of the waveforms of FIG. 11 is similar to thewaveforms shown in FIG. 9 and will not be discussed here.

As illustrated, the provision of the resistive elements R1 and R1-1 onboth sides of the NMOS transistors 62-1 to 62-N and the resistiveelements R2 and R2-1 on both sides of the PMOS transistors 63-1 to 63-Ngives further reduction in the rise of the Vss level and the fall of theVcc level, than the third embodiment.

Similar results could be obtained without the resistive elements R1-1and R2-1 if the resistances of the resistive elements R1 and R2 of FIG.7 were enlarged. However, if the resistive elements R1 and R2 wereformed of polysilicon or tungsten polycide as described in connectionwith the first embodiment, the length required could be to large, andthere is actually a restriction on this aspect. The resistive elementsR1-1 and R2-1 can be formed in place of the conductors connecting thememory cell arrays 60-1 and the transistors 62-1 and 63-1 (in otherwords, by forming the conductors of a material having a largeresistance). For this reason, providing the resistive elements R1 andR1-1 on both sides of the NMOS transistors 62-1 and the resistiveelements R2 and R2-1 on both sides of the PMOS transistors 63-1 to 63-Nwill require a smaller space to obtain the large resistance, therebyproperly preventing the rise in the Vss level and the fall in the Vcclevel.

Fifth Embodiment

FIG. 12 shows the pertinent portion of a fifth embodiment of theinvention. Elements identical to those in FIG. 7 are denoted byidentical reference numerals.

This semiconductor memory device differs from the third embodiment inthat a PMOS transistor 91 is provided in place of the resistive elementR1 and an NMOS transistor 92 is provided in place of the resistiveelement R2, and an NMOS transistor 93 serving as switching device isprovided in parallel with the PMOS transistor 91, and a PMOS transistor94 serving as switching device is provided in parallel with the NMOStransistor 92.

The PMOS transistor 91 has a threshold value Vtp, and its gate isconnected to the Vss so that it is kept on, functioning as a load MOStransistor causing a voltage drop corresponding to the threshold valueVtp. The NMOS transistor 92 has a threshold value Vtn, and its gate isconnected to the Vcc so that it is kept on, functioning as a load MOStransistor causing a voltage drop corresponding to the threshold valueto provide a potential (Vcc-Vtn) at its drain.

The NMOS transistor 93 and the PMOS transistor 94 serving as switchingdevices are transistors turned on and off by switching signals VG and VGoutput from a switching signal generating circuit 95. The switchingsignal generating circuit 95 outputs the switching signals VG and VGdelayed from the fall of the control signal (row address strobe signal)RAS by a predetermined time, and may be formed of a delay circuitcomprising plurality of stages of inverters. The timing at which theswitching signal VG rises is a little delayed from the rise of thecontrol signal SN.

FIG. 13 shows the waveform for explaining the operation of FIG. 12. ThePMOS transistor 91 and the NMOS transistor 92 are kept on, and when thecontrol signal SN rises and the control signal SP falls after thecontrol signal RAS falls, the sense amplifier drive NMOS transistor 62-1and PMOS transistor 63 are turned on. As a result, the sense latchsignal SLN flowing through the NMOS transistor 62-1 falls to thepotential (Vss+Vtp) and the sense latch signal signal SLP flowingthrough the PMOS transistor 63-1 rises to the potential (Vcc-Vtn).

When the switching signal VG output from the switching signal generatingcircuit 95 rises to the high level, the switching signal VG falls to thelow level. When the NMOS transistor 93 and the PMOS transistor 94 areturned on and the PMOS transistor 91 and the NMOS transistor 92 areshunted, and the sense latch signal SLN falls to the Vss level and thesense latch signal SLP rises to the Vcc level. With the variation of thesense latch signals SLN and SLP, the sense amplifier in the memory cellarray 60-1 is activated, and the potential difference on the pair of bitlines is detected and amplified.

In this fifth embodiment, with the switching of the NMOS transistor 93and the PMOS transistor 94, the sense latch signals SLN and SLP are madeto fall or rise in two steps, so the rapid change of the sense latchsignals SLN and SLP is alleviated, and the rapid change in the chargingand discharging currents during the operation of the sense amplifiersare restrained. For this reason, the power supply noise that occurs onthe power supply main lines 53a and 54a is divided into smaller piecesand the reduction in the data transfer speed which was a problemassociated with the third embodiment can be prevented.

Various modifications can be made to the embodiments described above.Examples of the modifications are set forth below.

(a) In FIG. 7, the resistive elements R1 can be provided on the side ofthe sources of the NMOS transistors 62-1 to 62-N and the resistiveelements R2 may be provided on the side of the sources of the PMOStransistors 63-1 to 63-N. Still similar merits to those of FIG. 7 areobtained.

(b) The first embodiment of FIG. 5 and the second embodiment of FIG. 6;and the third embodiment of FIG. 7 and the fourth embodiment of FIG. 10may be combined to form a semiconductor memory device. For instance, theresistive elements R1 in FIG. 7 may be replaced by the resistiveelements R11 to R1N in FIG. 5, and the resistive elements R2 in FIG. 7may be replaced by the resistive elements R21 to R2N in FIG. 1. Notethat the difference between the resistive elements R1, R2 and theresistive elements R11 to R1N, R21 to R2N is their resistance values, orthe manner in which their resistance values are determined. Then, thedifference in the operation margin between the memory cell arrays 60-1to 60-N in FIG. 7 can be reduced, and the setting of the control timingfor reading, writing etc. can be facilitated.

(c) The PMOS transistor 91 in FIG. 12 may be replaced by the resistiveelement R11 to R1N in FIG. 6, or by the resistive element R1 in FIG. 7or FIG. 10. In addition, the NMOS transistor 92 in FIG. 12 may bereplaced by the resistive element R21 to R2N in FIG. 6, or by theresistive elements R2 in FIG. 7 or FIG. 10. In addition, the switchingsignal generating circuit 95 in FIG. 12 may be so configured as toproduce the switching signals VG and VG using signals other than thecontrol signal RAS, e.g., the control signal SN, SP, or other signals.

Sixth Embodiment

FIG. 14 is a diagram showing the pertinent portion of the semiconductormemory device of a sixth embodiment of the invention.

This semiconductor memory device is a dynamic RAM provided with a Vsspower supply pad 160 and a Vcc power supply pad 170. Connected to thepower supply pad 160 are a Vss power supply main line 161a and anotherVss power supply line 163. Connected to the power supply pad 170 are aVcc power supply lines 171a and another Vcc power supply line 172. Thepower supply main lines 161a and 171a are dedicated to the drive ofsense amplifiers in order to prevent the adverse effect of the powersupply noise at the time of the operation of the sense amplifiers.Connected to the other power supply lines 162 and 172 are peripheralcircuits of the semiconductor memory device, including the inputinitial-stage circuits.

Connected to the power supply main line 161a are drains of NMOStransistors 164₁ to 164_(N), sources of which are connected to commonnodes N1 for activation of a plurality of sense amplifiers. Connected tothe power supply main line 171a are drains of NMOS transistors 174₁ to174_(N), sources of which are connected to common nodes N2 foractivation of the plurality of sense amplifiers. The NMOS transistors164₁ to 164_(N) are turned on and off by a control signal SN output froma control circuit (not shown), but similar to that described earlier inconnection with other embodiments. The PMOS transistors 174₁ to 174_(N)are turned on and off by a control signal SP output from the controlcircuit. Memory cell arrays 180₁ to 180_(N) are connected between thecommon nodes N1 and N2.

The Vss power supply main line 161a has line resistance r, and the powersupply resistance over the power supply main line 161a is increased withthe distance from the Vss power supply pad 160. Similarly, the Vcc powersupply main lines 171a has line resistance r, and the power supplyresistance over the power supply line 171a is increased with thedistance from the Vcc power supply pad 170.

In this embodiment, the mutual conductance of the NMOS transistor164_(N) which is located farthest from Vss pad 160 among the NMOStransistors 164₁ to 164_(N), is made equal to that of the NMOStransistor (11-1 to 11-N) in the prior art of FIG. 2, and as theresistance over the power supply main line 161a is increased, the mutualconductance is varied such that:

    MN.sub.1 >MN.sub.2 > . . . >MN.sub.N-1 >MN.sub.N

where MN₁ to MN_(N) respectively represent the mutual conductances ofthe NMOS transistors 164₁ to 164_(N).

Further, the mutual conductance of the PMOS transistors 174₁ to 174_(N)is so set that the PMOS transistor 174₁ located farthest from Vcc pad170 is made equal to that of the PMOS transistor (12-1 to 12-N) in theprior art of FIG. 2, and as the power supply resistance over the powersupply main line 161a is increased, the mutual conductance is variedsuch that:

    MP.sub.N >MP.sub.N-1 > . . . >MP.sub.2 >MP.sub.1

where MP_(N) to MP₁ respectively represent the mutual conductances ofthe PMOS transistors 174₁ to 174_(N).

The mutual conductances of the transistors can be adjusted by, forexample, varying the gate width.

Like the example of FIG. 8, each of the memory cell arrays 180₁ to180_(N) in FIG. 14 is provided with a plurality of word lines WL₁ toWL_(Q), and a plurality of pairs of bit lines BL₁, BL₁ to BL_(P),BL_(P), and memory cells 70₁₁ to 70_(PQ) connected at theirintersections. Connected between the pairs of bit lines BL₁, BL₁ toBL_(P), BL_(P) are sense amplifiers 60b₁ to 60b_(P).

Data reading operation of the above semiconductor memory device issimilar to described in connection with the earlier describedembodiments.

Let us assume, for example that data "1" is stored in the memory cell70₁₁ in FIG. 8, and is read from it, the word line WL₁ is raised fromthe low level to the high level by a row decode selection signal XD₁.Then the NMOS transistor 70a in the memory cell 70₁₁ is turned on, thedata "1" stored in the capacitor 70b is transmitted to the bit line BL₁and a slight potential difference is created between the pair of bitlines BL₁ and BL₁. At the same time, data in the memory cells 70₂₁ to70_(P1) connected to the same word line WL₁ are transmitted to the bitlines BL₂ to BL_(P). When the control signal SN of FIG. 14 is raisedfrom the low level to the high level, and at the same time the controlsignal SP is lowered from the high level to the low level, the NMOStransistors 164₁ to 164_(N) and the PMOS transistors 174₁ to 174_(N) areturned on. The common nodes N1 on the side of the sources of the NMOStransistors 164₁ to 164_(N) are then lowered to the low level, and thecommon nodes N2 on the sides of the sources of the PMOS transistors 174₁to 174_(N) are raised to the high level, and the sense amplifiers 60b₁to 60b_(P) are thereby activated.

When the sense amplifiers 60b₁ to 60b_(P) are activated, the senseamplifier 60b₁ amplifies the potential difference between the pair ofbit lines BL₁ and BL₁ in FIG. 8. A charging current flows from the powersupply line 171 through the sense amplifier 60b₁ to the bit line BL₁,and a discharging current for the bit line BL₁ flows through the senseamplifier 60b₁ to the power supply line 161. At the same time, the senseamplifiers 60b₂ to 60b_(P) amplify the potential differences on the bitline pairs BL₂, BL₂ to BL_(P), BL_(P), and charging and dischargingcurrents flow to and from these bit lines.

The potential difference between the pair of the bit lines BL₁ and BL₁amplified by the sense amplifier 60b₁ is passed through the transfergate 82₁ that is selected by the row decode selection signal YD₁ to thedata bus DB, DB. Thus, data of the memory cell 70₁₁ is selectively read.

FIG. 15A and FIG. 15B show the waveforms on the sense amplifieractivation common nodes N1 and N2, in the vicinities of the power supplypads 160 and 170, for both the present embodiment and in the vicinitiesof the power supply pads 1 and 2 in the prior art. The solid line showsthe waveforms of the present embodiment, and the broken line shows thewaveforms of the prior art.

To drive the sense amplifiers in the memory cell arrays 180₁ to 180_(N),the NMOS transistors 164₁ to 164_(N) and the PMOS transistors 174₁ to174_(N) are turned on to vary the common nodes N1 to the low level andthe common nodes N2 to the high level. In the present embodiment, thegate width of the NMOS transistor 164₁ and the PMOS transistor 174_(N)connected to the location where the resistance over the power supplyline 161 or 171 is small, is set equal to or smaller than that of thetransistor in the prior art, so the on-resistance is larger and thecharging and discharging currents flowing instantly through the NMOStransistor 164₁ and 174₁ are reduced. As a result, as shown in FIG. 15Aand FIG. 15B, the Vss and Vcc power supply noises can be restrained.Moreover, the noise level during the operation of the memory cell array180₁ and the noise level during the operation of the memory cell array180_(N) are about equal, so the difference in the noise level dependingon the memory cell array which is operating can be reduced.

Accordingly, the difference and decline of the operation margin of theperipheral circuit including the input initial-stage connected to otherpower supply lines 162 and 172 depending on the operating memory cellarray (180₁ to 180_(N)) can be eliminated. Adverse effects such asmalfunctions of the peripheral circuits due to the power supply noisecan be properly prevented, and the setting of the threshold value in theinput Initial-stage circuits is facilitated.

Various modifications can be made to the embodiment described above.Examples of the modifications are set forth below.

(a) In the above embodiment, the NMOS transistors 164₁ to 164_(N) andthe PMOS transistors 174₁ to 174_(N) have varied gate width depending onthe resistance of the power supply main lines 161a and 171a. But it isalso possible to vary, with the resistance with the power supply line,the mutual conductance by varying other transistor characteristics suchas the gate length. Moreover, the NMOS transistors 164₁ to 164_(N) andthe PMOS transistors 174₁ to 174_(N) may be formed of other transistorswith the polarity of the power supply altered.

(b) In FIG. 14, the number of the power supply lines 161a and 162, and171a and 172 connected to each power supply pad is 2. But this may beany other number depending on the circuit configuration of thesemiconductor memory device. The memory cell arrays 180₁ to 180_(N) mayhave configurations other than that shown in FIG. 3. The invention maybe applied to static RAM or other types of semiconductor memory devices.Various other modifications are possible.

Merits of the invention are summarized below.

According to the first and second embodiments of FIG. 5 and FIG. 6, thepower supply line comprises a main line connected to the power supply,and auxiliary power lines within the respective memory cell arrays, andthe main line is disposed along the memory cell arrays, while theauxiliary lines are disposed within the memory cell arrays, and the mainline and the auxiliary lines are connected via resistive elements. Theresistance of the resistive elements are set higher than the resistanceof the main line. It is therefore possible to reduce the differencebetween the resistances from the power supply to the respective memorycell arrays. The difference in the operation margin between the memorycell arrays due to the difference in the resistance can therefore bereduced, and the setting of the control timing for reading, writing,etc. is facilitated.

According to the third and fourth embodiments of FIG. 7 and FIG. 10,resistive elements and the sense amplifier drive transistors connectedin series are provided, so that the charging and discharging currentsflowing therethrough when the sense amplifiers conduct can be reduced byvirtue of the resistive elements, and the rise or fall in the powersupply voltage can be reduced. For this reason, the delay in the accessin the operation of the circuit after the sense latch, and reduction inthe margin, such as the TTL margin can be prevented.

According to the fifth embodiment of FIG. 12, the switching devices areprovided in parallel with the resistive elements. By turning on and offthe switching elements responsive to a switching signal, the rapidchange in the charging and discharging currents during the senseamplifier operation can be restrained. For this reason, the power supplynoise can be reduced, and the reduction in the data transfer speed canbe prevented, and the access time can be shortened.

According to the sixth embodiment of FIG. 14, the mutual conductance ofthe transistor for driving sense amplifiers is set in accordance withthe resistance of the power supply line. For example, it is set small ata location were the resistance of the power supply line is small.Accordingly, the noise level in the vicinity of the power supply padconnected to the power supply line at the time of the operation of thesense amplifier can be reduced, and the operation margin in theperipheral circuit including the input initial-stage circuits driven bythe same power supply pad can be improved. Moreover, the level of thenoise created on the power supply line is uniform regardless of whichtransistor is operating. As a result, the setting of the threshold valuein the input initial-stage circuits which operate on the TTL logic isfacilitated.

What is claimed is:
 1. A semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells of the array are connected is detected and amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, comprising:a plurality of sense amplifier drive transistors, each respective transistor being connected between said common node in each respective memory cell array and said power supply line, each transistor being turned on and off by a control signal; and a plurality of resistors, each respective resistor being connected between one of said sense amplifier drive transistors and said power supply line.
 2. The semiconductor memory device of claim 1, further comprising a plurality of additional resistors, each additional resistor being inserted between a respective sense amplifier drive transistor and the common node in each memory cell array.
 3. A semiconductor memory device comprising:a plurality of memory cells connected at the intersections of a plurality of word lines and a plurality of pairs of bit lines; a plurality of sense amplifiers for detecting and amplifying the potential difference between the corresponding pairs of bit lines; a plurality of transistors turned on by a control signal to connect said plurality of sense amplifiers to a power supply line; wherein said plurality of transistors have mutual conductance which differ depending on the resistance over the power supply line.
 4. The semiconductor memory device of claim 3, further comprising:a power supply pad for connection with an external power supply; wherein said power supply line is connected to said power supply pad.
 5. The semiconductor memory device of claim 4, in which the mutual conductance of a transistor of the plurality of transistors increases as a distance of the transistor from the power supply pad increases.
 6. A semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells of the array are connected is detected and amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, in which:said common node in each memory cell array is connected to said power supply line via a series connection of a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal; and in which a switching means which is turned on and off by a switching signal delayed from said control signal by a predetermined time is connected in parallel with said resistive element.
 7. A semiconductor memory device having a plurality of memory cell arrays connected to a power supply, each memory cell array including:a pair of bit lines connected to a memory cell; a sense amplifier for amplifying a potential difference between the pair of bit lines in response to a sense latch signal applied to a common node; a sense amplifier transistor connected between said common node and said power supply, which is turned on and off by a control signal; and a resistor connected between said sense amplifier transistor and said power supply.
 8. A semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells of the array are connected is detected and amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, comprising:a plurality of sense amplifier drive transistors, each respective transistor being connected between said common node in each respective memory cell array and said power supply line, each transistor being turned on and off by a control signal; and a plurality of MOS transistors, each respective MOS transistor being connected between a sense amplifier drive transistor and said power supply line, a fixed potential being applied to a gate of each of said MOS transistors.
 9. The semiconductor memory device of claim 8, in which a plurality of switching means, which are turned on and off by a switching signal delayed from said control signal by a predetermined time, are respectively connected in parallel with each of the plurality of MOS transistors. 